About the role DroneShield is seeking a Mid-level FPGA Engineer to join our team in Sydney, Australia, reporting to the Team Lead, FPGA. This role focuses on developing and scaling drone recognition and disruption capabilities using software-defined radios (SDRs). You will design and implement FPGA-based systems for real-time Digital Signal Processing, translating complex algorithms into production-grade firmware. The role also involves building robust verification frameworks, including cocotb simulations and hardware-in-the-loop testing, integrated into CI/CD pipelines. Responsibilities, Duties and Expectations Design, development, document and implementation of FPGA-based systems to support real-time Digital Signal Processing Architect and automate comprehensive test procedures - develop cocotb simulation models and hardware in the loop tests to be included in CI/CD pipeline integration Develop supporting C++ firmware for embedded systems, including control, configuration, and communication interfaces Qualifications, Experience and Skills BS/BE degree in Electronic Engineering, similar technical field of study or equivalent practical experience 2 to 5 years of experience working with FPGAs Strong experience with programming, debugging, and verifying Verilog, VHDL or SystemVerilog Experience writing modern C++ (C++14/17/20) for embedded firmware Experience with synthesis and timing closure on resource constrained FPGAs FPGA development experience using tools such as Vivado (preferable), Quartus, Vitis etc Experience with designing and implementing high-throughput, low-latency and fully pipelined FPGA architectures Nice to have: Experience working in a Linux environment Experience with RFSoC and software defined radios (SDR) is highly desirable Familiarity with scripting languages (Python Preferable) Experience working with PCB schematics, board bring-ups and debugging hardware is highly desirable Strong background and experience in Digital Signal Processing A general RF background and knowledge of RF transmission protocols and general principals is desirable Experience with AXI-lite and DMA transfers between PL and PS domains of AMD FPGAs Note for recruitment agencies: We do not accept unsolicited candidates from external recruiters unless specifically instructed. 631